diff options
| author | Sven Schnelle <svens@stackframe.org> | 2019-03-11 20:16:01 +0100 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2019-03-12 09:13:43 -0700 |
| commit | 32dc75698c848d11a087c77570ac0cd954e0bb20 (patch) | |
| tree | 6d13f249407f0a4d6544399469c60ab15e8e69b8 /target/hppa | |
| parent | d5de20bd84ae3a6f6c194f0088cfcb4d4f6af602 (diff) | |
target/hppa: exit TB if either Data or Instruction TLB changes
The current code assumes that we don't need to exit the TB
if a Data Cache Flush or Insert has happend. However, as we
have a shared Data/Instruction TLB, a Data cache flush also
flushes Instruction TLB entries, and a Data cache TLB insert
might also evict a Instruction TLB entry.
So exit the TB in all cases if Instruction translation is enabled.
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Message-Id: <20190311191602.25796-11-svens@stackframe.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'target/hppa')
| -rw-r--r-- | target/hppa/translate.c | 7 |
1 files changed, 3 insertions, 4 deletions
diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 70a7cd4a89..35c504087f 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -2482,9 +2482,8 @@ static bool trans_ixtlbx(DisasContext *ctx, arg_ixtlbx *a) gen_helper_itlbp(cpu_env, addr, reg); } - /* Exit TB for ITLB change if mmu is enabled. This *should* not be - the case, since the OS TLB fill handler runs with mmu disabled. */ - if (!a->data && (ctx->tb_flags & PSW_C)) { + /* Exit TB for TLB change if mmu is enabled. */ + if (ctx->tb_flags & PSW_C) { ctx->base.is_jmp = DISAS_IAQ_N_STALE; } return nullify_end(ctx); @@ -2511,7 +2510,7 @@ static bool trans_pxtlbx(DisasContext *ctx, arg_pxtlbx *a) } /* Exit TB for TLB change if mmu is enabled. */ - if (!a->data && (ctx->tb_flags & PSW_C)) { + if (ctx->tb_flags & PSW_C) { ctx->base.is_jmp = DISAS_IAQ_N_STALE; } return nullify_end(ctx); |