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| author | Richard Henderson <richard.henderson@linaro.org> | 2017-11-01 05:03:09 -0700 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2018-01-31 05:30:50 -0800 |
| commit | 5eecd37a931e04b229fe6b695781932161a38c0a (patch) | |
| tree | 2b05715dc7f47488847e9a089517cc57e7224f8b /target/hppa/translate.c | |
| parent | 46559e8184b23e539912bb78764e662b5eabb537 (diff) | |
target/hppa: Increase number of temp regs
HP-UX 10.20 CD contains "add r0, r0, r27" in a delay slot,
which uses at least 5 temps.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'target/hppa/translate.c')
| -rw-r--r-- | target/hppa/translate.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target/hppa/translate.c b/target/hppa/translate.c index b6b7262e53..6ff82d3e9c 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -277,7 +277,7 @@ typedef struct DisasContext { TCGv_reg iaoq_n_var; int ntempr, ntempl; - TCGv_reg tempr[4]; + TCGv_reg tempr[8]; TCGv_tl templ[4]; DisasCond null_cond; |