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authorRichard Henderson <richard.henderson@linaro.org>2018-03-24 17:15:03 +0800
committerRichard Henderson <richard.henderson@linaro.org>2018-03-26 22:56:57 +0800
commitebd0e151149a6280ea9f4cd9638aea517bb3238b (patch)
treeebfdee9f5bf4d9e6962e50e82be9d7de3c3a2de5 /target/hppa/cpu.h
parent2ffd221d07a671f72354a063d3080f244ec80b20 (diff)
target/hppa: Include priv level in user-only iaoq
A recent glibc change relies on the fact that the iaoq must be 3, and computes an address based on that. QEMU had been ignoring the priv level for user-only, which produced an incorrect address. Reported-by: John David Anglin <dave.anglin@bell.net> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'target/hppa/cpu.h')
-rw-r--r--target/hppa/cpu.h4
1 files changed, 2 insertions, 2 deletions
diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h
index 19dd12a93e..861bbb1f16 100644
--- a/target/hppa/cpu.h
+++ b/target/hppa/cpu.h
@@ -305,8 +305,8 @@ static inline void cpu_get_tb_cpu_state(CPUHPPAState *env, target_ulong *pc,
incomplete virtual address. This also means that we must separate
out current cpu priviledge from the low bits of IAOQ_F. */
#ifdef CONFIG_USER_ONLY
- *pc = env->iaoq_f;
- *cs_base = env->iaoq_b;
+ *pc = env->iaoq_f & -4;
+ *cs_base = env->iaoq_b & -4;
#else
/* ??? E, T, H, L, B, P bits need to be here, when implemented. */
flags |= env->psw & (PSW_W | PSW_C | PSW_D);