diff options
author | Taylor Simpson <tsimpson@quicinc.com> | 2021-10-11 11:48:52 -0500 |
---|---|---|
committer | Taylor Simpson <tsimpson@quicinc.com> | 2021-10-28 22:22:41 -0500 |
commit | f448397a512189e726f5e8026c89ce7fc4392377 (patch) | |
tree | 6493e86e616c13fa261bf95dd1cadafc9ef32978 /target/hexagon | |
parent | c52d69e7dbaaed0ffdef8125e79218672c30161d (diff) |
Hexagon (target/hexagon) more tcg_constant_*
Change additional tcg_const_tl to tcg_constant_tl
Note that gen_pred_cancal had slot_mask initialized with tcg_const_tl.
However, it is not constant throughout, so we initialize it with
tcg_temp_new and replace the first use with the constant value.
Inspired-by: Richard Henderson <richard.henderson@linaro.org>
Inspired-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Diffstat (limited to 'target/hexagon')
-rw-r--r-- | target/hexagon/gen_tcg.h | 9 | ||||
-rwxr-xr-x | target/hexagon/gen_tcg_funcs.py | 11 | ||||
-rw-r--r-- | target/hexagon/macros.h | 7 | ||||
-rw-r--r-- | target/hexagon/translate.c | 3 |
4 files changed, 9 insertions, 21 deletions
diff --git a/target/hexagon/gen_tcg.h b/target/hexagon/gen_tcg.h index 0361564104..c6f0879b6e 100644 --- a/target/hexagon/gen_tcg.h +++ b/target/hexagon/gen_tcg.h @@ -66,11 +66,10 @@ } while (0) #define GET_EA_pci \ do { \ - TCGv tcgv_siV = tcg_const_tl(siV); \ + TCGv tcgv_siV = tcg_constant_tl(siV); \ tcg_gen_mov_tl(EA, RxV); \ gen_helper_fcircadd(RxV, RxV, tcgv_siV, MuV, \ hex_gpr[HEX_REG_CS0 + MuN]); \ - tcg_temp_free(tcgv_siV); \ } while (0) #define GET_EA_pcr(SHIFT) \ do { \ @@ -557,7 +556,7 @@ #define fGEN_TCG_A4_addp_c(SHORTCODE) \ do { \ TCGv_i64 carry = tcg_temp_new_i64(); \ - TCGv_i64 zero = tcg_const_i64(0); \ + TCGv_i64 zero = tcg_constant_i64(0); \ tcg_gen_extu_i32_i64(carry, PxV); \ tcg_gen_andi_i64(carry, carry, 1); \ tcg_gen_add2_i64(RddV, carry, RssV, zero, carry, zero); \ @@ -565,14 +564,13 @@ tcg_gen_extrl_i64_i32(PxV, carry); \ gen_8bitsof(PxV, PxV); \ tcg_temp_free_i64(carry); \ - tcg_temp_free_i64(zero); \ } while (0) /* r5:4 = sub(r1:0, r3:2, p1):carry */ #define fGEN_TCG_A4_subp_c(SHORTCODE) \ do { \ TCGv_i64 carry = tcg_temp_new_i64(); \ - TCGv_i64 zero = tcg_const_i64(0); \ + TCGv_i64 zero = tcg_constant_i64(0); \ TCGv_i64 not_RttV = tcg_temp_new_i64(); \ tcg_gen_extu_i32_i64(carry, PxV); \ tcg_gen_andi_i64(carry, carry, 1); \ @@ -582,7 +580,6 @@ tcg_gen_extrl_i64_i32(PxV, carry); \ gen_8bitsof(PxV, PxV); \ tcg_temp_free_i64(carry); \ - tcg_temp_free_i64(zero); \ tcg_temp_free_i64(not_RttV); \ } while (0) diff --git a/target/hexagon/gen_tcg_funcs.py b/target/hexagon/gen_tcg_funcs.py index ca8a801baa..e3d59dd552 100755 --- a/target/hexagon/gen_tcg_funcs.py +++ b/target/hexagon/gen_tcg_funcs.py @@ -279,15 +279,12 @@ def gen_helper_call_opn(f, tag, regtype, regid, toss, numregs, i): print("Bad register parse: ",regtype,regid,toss,numregs) def gen_helper_decl_imm(f,immlett): - f.write(" TCGv tcgv_%s = tcg_const_tl(%s);\n" % \ + f.write(" TCGv tcgv_%s = tcg_constant_tl(%s);\n" % \ (hex_common.imm_name(immlett), hex_common.imm_name(immlett))) def gen_helper_call_imm(f,immlett): f.write(", tcgv_%s" % hex_common.imm_name(immlett)) -def gen_helper_free_imm(f,immlett): - f.write(" tcg_temp_free(tcgv_%s);\n" % hex_common.imm_name(immlett)) - def genptr_dst_write_pair(f, tag, regtype, regid): if ('A_CONDEXEC' in hex_common.attribdict[tag]): f.write(" gen_log_predicated_reg_write_pair(%s%sN, %s%sV, insn->slot);\n" % \ @@ -401,7 +398,7 @@ def gen_tcg_func(f, tag, regs, imms): for immlett,bits,immshift in imms: gen_helper_decl_imm(f,immlett) if hex_common.need_part1(tag): - f.write(" TCGv part1 = tcg_const_tl(insn->part1);\n") + f.write(" TCGv part1 = tcg_constant_tl(insn->part1);\n") if hex_common.need_slot(tag): f.write(" TCGv slot = tcg_constant_tl(insn->slot);\n") f.write(" gen_helper_%s(" % (tag)) @@ -424,10 +421,6 @@ def gen_tcg_func(f, tag, regs, imms): if hex_common.need_slot(tag): f.write(", slot") if hex_common.need_part1(tag): f.write(", part1" ) f.write(");\n") - if hex_common.need_part1(tag): - f.write(" tcg_temp_free(part1);\n") - for immlett,bits,immshift in imms: - gen_helper_free_imm(f,immlett) ## Write all the outputs for regtype,regid,toss,numregs in regs: diff --git a/target/hexagon/macros.h b/target/hexagon/macros.h index 44e9b857b5..5c19cdeb00 100644 --- a/target/hexagon/macros.h +++ b/target/hexagon/macros.h @@ -187,10 +187,10 @@ #ifdef QEMU_GENERATE static inline void gen_pred_cancel(TCGv pred, int slot_num) { - TCGv slot_mask = tcg_const_tl(1 << slot_num); + TCGv slot_mask = tcg_temp_new(); TCGv tmp = tcg_temp_new(); TCGv zero = tcg_constant_tl(0); - tcg_gen_or_tl(slot_mask, hex_slot_cancelled, slot_mask); + tcg_gen_ori_tl(slot_mask, hex_slot_cancelled, 1 << slot_num); tcg_gen_andi_tl(tmp, pred, 1); tcg_gen_movcond_tl(TCG_COND_EQ, hex_slot_cancelled, tmp, zero, slot_mask, hex_slot_cancelled); @@ -498,10 +498,9 @@ static inline TCGv gen_read_ireg(TCGv result, TCGv val, int shift) #define fPM_M(REG, MVAL) tcg_gen_add_tl(REG, REG, MVAL) #define fPM_CIRI(REG, IMM, MVAL) \ do { \ - TCGv tcgv_siV = tcg_const_tl(siV); \ + TCGv tcgv_siV = tcg_constant_tl(siV); \ gen_helper_fcircadd(REG, REG, tcgv_siV, MuV, \ hex_gpr[HEX_REG_CS0 + MuN]); \ - tcg_temp_free(tcgv_siV); \ } while (0) #else #define fEA_IMM(IMM) do { EA = (IMM); } while (0) diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c index 159931e8ee..724b4fc11e 100644 --- a/target/hexagon/translate.c +++ b/target/hexagon/translate.c @@ -487,9 +487,8 @@ static void gen_commit_packet(DisasContext *ctx, Packet *pkt) * process_store_log will execute the slot 1 store first, * so we only have to probe the store in slot 0 */ - TCGv mem_idx = tcg_const_tl(ctx->mem_idx); + TCGv mem_idx = tcg_constant_tl(ctx->mem_idx); gen_helper_probe_pkt_scalar_store_s0(cpu_env, mem_idx); - tcg_temp_free(mem_idx); } process_store_log(ctx, pkt); |