diff options
| author | Taylor Simpson <tsimpson@quicinc.com> | 2023-04-10 09:09:41 -0700 |
|---|---|---|
| committer | Taylor Simpson <tsimpson@quicinc.com> | 2023-04-21 09:32:52 -0700 |
| commit | a305a170398d80c08e19c2ef4c8637a4f4de50e1 (patch) | |
| tree | dab4ac994cd1ca8a5c528e0034d6544926ff0d97 /target/hexagon/macros.h | |
| parent | 111c529aa652fde71fe54a91776ffd166b724b42 (diff) | |
Hexagon (target/hexagon) Add overrides for cache/sync/barrier instructions
Most of these are not modelled in QEMU, so save the overhead of
calling a helper.
The only exception is dczeroa. It assigns to hex_dczero_addr, which
is handled during packet commit.
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230410202402.2856852-1-tsimpson@quicinc.com>
Diffstat (limited to 'target/hexagon/macros.h')
| -rw-r--r-- | target/hexagon/macros.h | 18 |
1 files changed, 4 insertions, 14 deletions
diff --git a/target/hexagon/macros.h b/target/hexagon/macros.h index 9ddfc91b1d..3e162de3a7 100644 --- a/target/hexagon/macros.h +++ b/target/hexagon/macros.h @@ -659,20 +659,10 @@ static inline TCGv gen_read_ireg(TCGv result, TCGv val, int shift) fEXTRACTU_BITS(env->gpr[HEX_REG_##REG], \ reg_field_info[FIELD].width, \ reg_field_info[FIELD].offset) -#define fBARRIER() -#define fSYNCH() -#define fISYNC() -#define fDCFETCH(REG) \ - do { (void)REG; } while (0) /* Nothing to do in qemu */ -#define fICINVA(REG) \ - do { (void)REG; } while (0) /* Nothing to do in qemu */ -#define fL2FETCH(ADDR, HEIGHT, WIDTH, STRIDE, FLAGS) -#define fDCCLEANA(REG) \ - do { (void)REG; } while (0) /* Nothing to do in qemu */ -#define fDCCLEANINVA(REG) \ - do { (void)REG; } while (0) /* Nothing to do in qemu */ - -#define fDCZEROA(REG) do { env->dczero_addr = (REG); } while (0) + +#ifdef QEMU_GENERATE +#define fDCZEROA(REG) tcg_gen_mov_tl(hex_dczero_addr, (REG)) +#endif #define fBRANCH_SPECULATE_STALL(DOTNEWVAL, JUMP_COND, SPEC_DIR, HINTBITNUM, \ STRBITNUM) /* Nothing */ |