diff options
author | Taylor Simpson <ltaylorsimpson@gmail.com> | 2023-12-10 15:07:04 -0700 |
---|---|---|
committer | Brian Cain <bcain@quicinc.com> | 2024-01-21 22:01:42 -0800 |
commit | 421b53d589e2a714b3f3175dddedda9755e83387 (patch) | |
tree | 7b88c261dfcf50614309f70d2efd22e5f40aba21 /target/hexagon/gen_tcg_funcs.py | |
parent | ccdae09a8054731fbf49d5f223ff1903408a5ac3 (diff) |
Hexagon (target/hexagon) Clean up handling of modifier registers
Currently, the register number (MuN) for modifier registers is the
modifier register number rather than the index into hex_gpr. This
patch changes MuN to the hex_gpr index, which is consistent with
the handling of control registers.
Note that HELPER(fcircadd) needs the CS register corresponding to the
modifier register specified in the instruction. We create a TCGv
variable "CS" to hold the value to pass to the helper.
Reviewed-by: Brian Cain <bcain@quicinc.com>
Signed-off-by: Taylor Simpson <ltaylorsimpson@gmail.com>
Message-Id: <20231210220712.491494-2-ltaylorsimpson@gmail.com>
Signed-off-by: Brian Cain <bcain@quicinc.com>
Diffstat (limited to 'target/hexagon/gen_tcg_funcs.py')
-rwxr-xr-x | target/hexagon/gen_tcg_funcs.py | 13 |
1 files changed, 9 insertions, 4 deletions
diff --git a/target/hexagon/gen_tcg_funcs.py b/target/hexagon/gen_tcg_funcs.py index f5246cee6d..02d93bc5ce 100755 --- a/target/hexagon/gen_tcg_funcs.py +++ b/target/hexagon/gen_tcg_funcs.py @@ -99,10 +99,15 @@ def genptr_decl(f, tag, regtype, regid, regno): hex_common.bad_register(regtype, regid) elif regtype == "M": if regid == "u": - f.write(f" const int {regtype}{regid}N = " f"insn->regno[{regno}];\n") f.write( - f" TCGv {regtype}{regid}V = hex_gpr[{regtype}{regid}N + " - "HEX_REG_M0];\n" + f" const int {regN} = insn->regno[{regno}] + HEX_REG_M0;\n" + ) + f.write( + f" TCGv {regtype}{regid}V = hex_gpr[{regN}];\n" + ) + f.write( + f" TCGv CS G_GNUC_UNUSED = " + f"hex_gpr[{regN} - HEX_REG_M0 + HEX_REG_CS0];\n" ) else: hex_common.bad_register(regtype, regid) @@ -528,7 +533,7 @@ def gen_tcg_func(f, tag, regs, imms): ): declared.append(f"{regtype}{regid}V") if regtype == "M": - declared.append(f"{regtype}{regid}N") + declared.append("CS") elif hex_common.is_new_val(regtype, regid, tag): declared.append(f"{regtype}{regid}N") else: |