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| author | Taylor Simpson <tsimpson@quicinc.com> | 2021-10-04 19:12:31 -0500 |
|---|---|---|
| committer | Taylor Simpson <tsimpson@quicinc.com> | 2021-10-28 22:22:49 -0500 |
| commit | b9dd6ff91d29b9e38afd7facf1d683f34bd1ec10 (patch) | |
| tree | 3545ca5315862dad7b2d90b681cc3f016bc71f1f /target/hexagon/attribs_def.h.inc | |
| parent | f448397a512189e726f5e8026c89ce7fc4392377 (diff) | |
Hexagon (target/hexagon) put writes to USR into temp until commit
Change SET_USR_FIELD to write to hex_new_value[HEX_REG_USR] instead
of hex_gpr[HEX_REG_USR].
Then, we need code to mark the instructions that can set implicitly
set USR
- Macros added to hex_common.py
- A_FPOP added in translate.c
Test case added in tests/tcg/hexagon/overflow.c
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Diffstat (limited to 'target/hexagon/attribs_def.h.inc')
| -rw-r--r-- | target/hexagon/attribs_def.h.inc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/target/hexagon/attribs_def.h.inc b/target/hexagon/attribs_def.h.inc index 381550909d..e44a7ead16 100644 --- a/target/hexagon/attribs_def.h.inc +++ b/target/hexagon/attribs_def.h.inc @@ -64,6 +64,7 @@ DEF_ATTRIB(IMPLICIT_WRITES_P1, "Writes Predicate 1", "", "UREG.P1") DEF_ATTRIB(IMPLICIT_WRITES_P2, "Writes Predicate 1", "", "UREG.P2") DEF_ATTRIB(IMPLICIT_WRITES_P3, "May write Predicate 3", "", "UREG.P3") DEF_ATTRIB(IMPLICIT_READS_PC, "Reads the PC register", "", "") +DEF_ATTRIB(IMPLICIT_WRITES_USR, "May write USR", "", "") DEF_ATTRIB(WRITES_PRED_REG, "Writes a predicate register", "", "") DEF_ATTRIB(CRSLOT23, "Can execute in slot 2 or slot 3 (CR)", "", "") |