diff options
| author | Peter Maydell <peter.maydell@linaro.org> | 2019-04-29 17:35:58 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2019-04-29 17:35:58 +0100 |
| commit | 5bcf8ed9401e62c73158ba110864ee1375558bf7 (patch) | |
| tree | e2dd89a4d14dda037265098490ed736c0cbe4fe6 /target/arm | |
| parent | 79d77bcd366190a81d092177e4f84d34b7a56fc2 (diff) | |
target/arm: Make sure M-profile FPSCR RES0 bits are not settable
Enforce that for M-profile various FPSCR bits which are RES0 there
but have defined meanings on A-profile are never settable. This
ensures that M-profile code can't enable the A-profile behaviour
(notably vector length/stride handling) by accident.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20190416125744.27770-2-peter.maydell@linaro.org
Diffstat (limited to 'target/arm')
| -rw-r--r-- | target/arm/vfp_helper.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c index 2468fc1629..7a46d99148 100644 --- a/target/arm/vfp_helper.c +++ b/target/arm/vfp_helper.c @@ -105,6 +105,14 @@ void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val) val &= ~FPCR_FZ16; } + if (arm_feature(env, ARM_FEATURE_M)) { + /* + * M profile FPSCR is RES0 for the QC, STRIDE, FZ16, LEN bits + * and also for the trapped-exception-handling bits IxE. + */ + val &= 0xf7c0009f; + } + /* * We don't implement trapped exception handling, so the * trap enable bits, IDE|IXE|UFE|OFE|DZE|IOE are all RAZ/WI (not RES0!) |