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authorLluís Vilanova <vilanova@ac.upc.edu>2017-07-14 12:50:27 +0300
committerRichard Henderson <richard.henderson@linaro.org>2017-09-06 08:06:48 -0700
commit4013f7fc811e90b89da3a516dc71b01ca0e7e54e (patch)
tree5aee57cf44d1e7510e08c21be27c872eaaad1942 /target/arm
parentbe4079641f1bc755fc5d3ff194cf505c506227d8 (diff)
target/arm: [tcg] Port to disas_log
Incrementally paves the way towards using the generic instruction translation loop. Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu> Reviewed-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Alex Benneé <alex.benee@linaro.org> Message-Id: <150002582711.22386.191527630537864599.stgit@frigg.lan> [rth: Move tb->size computation and use that result.] Signed-off-by: Richard Henderson <rth@twiddle.net>
Diffstat (limited to 'target/arm')
-rw-r--r--target/arm/translate.c18
1 files changed, 13 insertions, 5 deletions
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 10527b50c8..2dca196e17 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -12171,6 +12171,15 @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
}
}
+static void arm_tr_disas_log(const DisasContextBase *dcbase, CPUState *cpu)
+{
+ DisasContext *dc = container_of(dcbase, DisasContext, base);
+
+ qemu_log("IN: %s\n", lookup_symbol(dc->base.pc_first));
+ log_target_disas(cpu, dc->base.pc_first, dc->base.tb->size,
+ dc->thumb | (dc->sctlr_b << 1));
+}
+
/* generate intermediate code for basic block 'tb'. */
void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)
{
@@ -12251,20 +12260,19 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)
gen_tb_end(tb, dc->base.num_insns);
+ tb->size = dc->pc - dc->base.pc_first;
+ tb->icount = dc->base.num_insns;
+
#ifdef DEBUG_DISAS
if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM) &&
qemu_log_in_addr_range(dc->base.pc_first)) {
qemu_log_lock();
qemu_log("----------------\n");
- qemu_log("IN: %s\n", lookup_symbol(dc->base.pc_first));
- log_target_disas(cs, dc->base.pc_first, dc->pc - dc->base.pc_first,
- dc->thumb | (dc->sctlr_b << 1));
+ arm_tr_disas_log(&dc->base, cs);
qemu_log("\n");
qemu_log_unlock();
}
#endif
- tb->size = dc->pc - dc->base.pc_first;
- tb->icount = dc->base.num_insns;
}
static const char *cpu_mode_names[16] = {