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authorRemi Denis-Courmont <remi.denis.courmont@huawei.com>2019-01-26 08:52:10 +0200
committerPeter Maydell <peter.maydell@linaro.org>2019-02-01 15:23:51 +0000
commitf6768aa1b4c6a80448eabd22bb9b4123c709caea (patch)
tree585951c8095ce4bd679387276a0739809cc28b7c /target/arm
parent87877543b14feebf1bc4fd336d41901b036acf98 (diff)
target/arm: fix AArch64 virtual address space size
Since QEMU does not support the ARMv8.2-LVA, Large Virtual Address, extension (yet), the VA address space is 48-bits plus a sign bit. User mode can only handle the positive half of the address space, so that makes a limit of 48 bits. (With LVA, it would be 53 and 52 bits respectively.) The incorrectly large address space conflicts with PAuth instructions, which use bits 48-54 and 56-63 for the pointer authentication code. This also conflicts with (as yet unsupported by QEMU) data tagging and with the ARMv8.5-MTE extension. Signed-off-by: Remi Denis-Courmont <remi.denis.courmont@huawei.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm')
-rw-r--r--target/arm/cpu.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 63934a200a..a68bcc9fed 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -2512,7 +2512,7 @@ bool write_cpustate_to_list(ARMCPU *cpu);
#if defined(TARGET_AARCH64)
# define TARGET_PHYS_ADDR_SPACE_BITS 48
-# define TARGET_VIRT_ADDR_SPACE_BITS 64
+# define TARGET_VIRT_ADDR_SPACE_BITS 48
#else
# define TARGET_PHYS_ADDR_SPACE_BITS 40
# define TARGET_VIRT_ADDR_SPACE_BITS 32