diff options
| author | Peter Maydell <peter.maydell@linaro.org> | 2023-01-30 18:24:43 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2023-02-03 12:59:22 +0000 |
| commit | 034bb45ac14602c757c1e9da32196ffa94459c79 (patch) | |
| tree | 835dcc3daae445db390af587b01d44fd9248b600 /target/arm | |
| parent | 049edada5e93df096c66a059e1171942238fc472 (diff) | |
target/arm: Disable HSTR_EL2 traps if EL2 is not enabled
The HSTR_EL2 register is not supposed to have an effect unless EL2 is
enabled in the current security state. We weren't checking for this,
which meant that if the guest set up the HSTR_EL2 register we would
incorrectly trap even for accesses from Secure EL0 and EL1.
Add the missing checks. (Other places where we look at HSTR_EL2
for the not-in-v8A bits TTEE and TJDBX are already checking that
we are in NS EL0 or EL1, so there we alredy know EL2 is enabled.)
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Fuad Tabba <tabba@google.com>
Message-id: 20230130182459.3309057-8-peter.maydell@linaro.org
Message-id: 20230127175507.2895013-8-peter.maydell@linaro.org
Diffstat (limited to 'target/arm')
| -rw-r--r-- | target/arm/helper.c | 2 | ||||
| -rw-r--r-- | target/arm/op_helper.c | 1 |
2 files changed, 2 insertions, 1 deletions
diff --git a/target/arm/helper.c b/target/arm/helper.c index 6f6772d8e0..6696686921 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11716,7 +11716,7 @@ static CPUARMTBFlags rebuild_hflags_a32(CPUARMState *env, int fp_el, DP_TBFLAG_A32(flags, VFPEN, 1); } - if (el < 2 && env->cp15.hstr_el2 && + if (el < 2 && env->cp15.hstr_el2 && arm_is_el2_enabled(env) && (arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) { DP_TBFLAG_A32(flags, HSTR_ACTIVE, 1); } diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index 7797a137af..dec03310ad 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -663,6 +663,7 @@ const void *HELPER(access_check_cp_reg)(CPUARMState *env, uint32_t key, * we only need to check here for traps from EL0. */ if (!is_a64(env) && arm_current_el(env) == 0 && ri->cp == 15 && + arm_is_el2_enabled(env) && (arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) { uint32_t mask = 1 << ri->crn; |