diff options
| author | Edgar E. Iglesias <edgar.iglesias@xilinx.com> | 2018-10-11 04:19:28 +0200 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2018-10-16 17:14:55 +0100 |
| commit | 86278c33d1d71196f5e22ce3ce82a1b34a199754 (patch) | |
| tree | c21458a6ec93c8f69f053568cff12dc74a27c77c /target/arm | |
| parent | 357aa01335bbf715b7ad1ef621e4bc96e2ffbe19 (diff) | |
target-arm: powerctl: Enable HVC when starting CPUs to EL2
When QEMU provides the equivalent of the EL3 firmware, we
need to enable HVCs in scr_el3 when turning on CPUs that
target EL2.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Message-id: 20181011021931.4249-10-edgar.iglesias@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm')
| -rw-r--r-- | target/arm/arm-powerctl.c | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/target/arm/arm-powerctl.c b/target/arm/arm-powerctl.c index ce55eeb682..2b856930fb 100644 --- a/target/arm/arm-powerctl.c +++ b/target/arm/arm-powerctl.c @@ -103,6 +103,16 @@ static void arm_set_cpu_on_async_work(CPUState *target_cpu_state, } else { /* Processor is not in secure mode */ target_cpu->env.cp15.scr_el3 |= SCR_NS; + + /* + * If QEMU is providing the equivalent of EL3 firmware, then we need + * to make sure a CPU targeting EL2 comes out of reset with a + * functional HVC insn. + */ + if (arm_feature(&target_cpu->env, ARM_FEATURE_EL3) + && info->target_el == 2) { + target_cpu->env.cp15.scr_el3 |= SCR_HCE; + } } /* We check if the started CPU is now at the correct level */ |