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authorPeter Maydell <peter.maydell@linaro.org>2018-08-20 11:24:32 +0100
committerPeter Maydell <peter.maydell@linaro.org>2018-08-20 11:24:32 +0100
commitd79e0c0608899428281a17c414ccf1a82d86ab85 (patch)
tree6a5a163286087e9ab61cf4a23d571c4f1cbb36e1 /target/arm
parentb5ede85bfb7ba1a8f6086494c82f400b29969f65 (diff)
target/arm: Implement AArch32 HVBAR
Implement the AArch32 HVBAR register; we can do this just by making the existing VBAR_EL2 regdefs be STATE_BOTH. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Luc Michel <luc.michel@greensocs.com> Message-id: 20180814124254.5229-5-peter.maydell@linaro.org
Diffstat (limited to 'target/arm')
-rw-r--r--target/arm/helper.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/target/arm/helper.c b/target/arm/helper.c
index a68577a06a..274fb21912 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -3750,7 +3750,7 @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
/* Used to describe the behaviour of EL2 regs when EL2 does not exist. */
static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = {
- { .name = "VBAR_EL2", .state = ARM_CP_STATE_AA64,
+ { .name = "VBAR_EL2", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0,
.access = PL2_RW,
.readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore },
@@ -3899,7 +3899,7 @@ static const ARMCPRegInfo el2_cp_reginfo[] = {
.opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 0,
.access = PL2_RW,
.fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_HYP]) },
- { .name = "VBAR_EL2", .state = ARM_CP_STATE_AA64,
+ { .name = "VBAR_EL2", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0,
.access = PL2_RW, .writefn = vbar_write,
.fieldoffset = offsetof(CPUARMState, cp15.vbar_el[2]),