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authorWei Huang <wei@redhat.com>2017-02-10 17:40:28 +0000
committerPeter Maydell <peter.maydell@linaro.org>2017-02-10 17:40:28 +0000
commitd6f02ce3b8a43ddd8f83553fe754a34b26fb273f (patch)
treef77a2d285bc9d20b66c3a11ed29c369b64c221a7 /target/arm
parente6ec54571e424bb1d6e50e32fe317c616cde3e05 (diff)
target-arm: Enable vPMU support under TCG mode
This patch contains several fixes to enable vPMU under TCG mode. It first removes the checking of kvm_enabled() while unsetting ARM_FEATURE_PMU. With it, the .pmu option can be used to turn on/off vPMU under TCG mode. Secondly the PMU node of DT table is now created under TCG. The last fix is to disable the masking of PMUver field of ID_AA64DFR0_EL1. Signed-off-by: Wei Huang <wei@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1486504171-26807-5-git-send-email-wei@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm')
-rw-r--r--target/arm/cpu.c2
-rw-r--r--target/arm/helper.c7
2 files changed, 2 insertions, 7 deletions
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 4ee250cec6..4a069f6985 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -781,7 +781,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
unset_feature(env, ARM_FEATURE_EL2);
}
- if (!cpu->has_pmu || !kvm_enabled()) {
+ if (!cpu->has_pmu) {
cpu->has_pmu = false;
unset_feature(env, ARM_FEATURE_PMU);
}
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 5358ac6054..47250bcf16 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -4633,12 +4633,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)
{ .name = "ID_AA64DFR0_EL1", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 0,
.access = PL1_R, .type = ARM_CP_CONST,
- /* We mask out the PMUVer field, because we don't currently
- * implement the PMU. Not advertising it prevents the guest
- * from trying to use it and getting UNDEFs on registers we
- * don't implement.
- */
- .resetvalue = cpu->id_aa64dfr0 & ~0xf00 },
+ .resetvalue = cpu->id_aa64dfr0 },
{ .name = "ID_AA64DFR1_EL1", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 1,
.access = PL1_R, .type = ARM_CP_CONST,