diff options
| author | Peter Maydell <peter.maydell@linaro.org> | 2019-06-11 16:39:51 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2019-06-13 15:14:06 +0100 |
| commit | b623d803dda805f07aadcbf098961fde27315c19 (patch) | |
| tree | 0d265674ab44439f5b0a48acf0af224201e1b596 /target/arm/vfp.decode | |
| parent | 386bba2368842fc74388a3c1651c6c0c0c70adbd (diff) | |
target/arm: Convert the VCVT-from-f16 insns to decodetree
Convert the VCVTT, VCVTB instructions that deal with conversion
from half-precision floats to f32 or 64 to decodetree.
Since we're no longer constrained to the old decoder's style
using cpu_F0s and cpu_F0d we can perform a direct 16 bit
load of the right half of the input single-precision register
rather than loading the full 32 bits and then doing a
separate shift or sign-extension.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'target/arm/vfp.decode')
| -rw-r--r-- | target/arm/vfp.decode | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/target/arm/vfp.decode b/target/arm/vfp.decode index 9db7aa7021..53d9544f7c 100644 --- a/target/arm/vfp.decode +++ b/target/arm/vfp.decode @@ -181,3 +181,9 @@ VCMP_sp ---- 1110 1.11 010 z:1 .... 1010 e:1 1.0 .... \ vd=%vd_sp vm=%vm_sp VCMP_dp ---- 1110 1.11 010 z:1 .... 1011 e:1 1.0 .... \ vd=%vd_dp vm=%vm_dp + +# VCVTT and VCVTB from f16: Vd format depends on size bit; Vm is always vm_sp +VCVT_f32_f16 ---- 1110 1.11 0010 .... 1010 t:1 1.0 .... \ + vd=%vd_sp vm=%vm_sp +VCVT_f64_f16 ---- 1110 1.11 0010 .... 1011 t:1 1.0 .... \ + vd=%vd_dp vm=%vm_sp |