diff options
| author | Peter Maydell <peter.maydell@linaro.org> | 2020-08-28 19:33:29 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2020-09-01 11:19:32 +0100 |
| commit | f61e5c43b86907dea17f431b528d806659d62bcb (patch) | |
| tree | c0a0f2e77f4b00d2c3f83647f1eaccac269ca32f /target/arm/vfp-uncond.decode | |
| parent | e4875e3bcc3a9c54d7e074c8f51e04c2e6364e2e (diff) | |
target/arm: Implement new VFP fp16 insn VMOVX
The fp16 extension includes a new instruction VMOVX, which copies the
upper 16 bits of a 32-bit source VFP register into the lower 16
bits of the destination and zeroes the high half of the destination.
Implement it.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200828183354.27913-21-peter.maydell@linaro.org
Diffstat (limited to 'target/arm/vfp-uncond.decode')
| -rw-r--r-- | target/arm/vfp-uncond.decode | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/target/arm/vfp-uncond.decode b/target/arm/vfp-uncond.decode index 39dc8f6373..8891ab3d54 100644 --- a/target/arm/vfp-uncond.decode +++ b/target/arm/vfp-uncond.decode @@ -75,5 +75,8 @@ VCVT 1111 1110 1.11 11 rm:2 .... 1010 op:1 1.0 .... \ VCVT 1111 1110 1.11 11 rm:2 .... 1011 op:1 1.0 .... \ vm=%vm_dp vd=%vd_sp sz=3 +VMOVX 1111 1110 1.11 0000 .... 1010 01 . 0 .... \ + vd=%vd_sp vm=%vm_sp + VINS 1111 1110 1.11 0000 .... 1010 11 . 0 .... \ vd=%vd_sp vm=%vm_sp |