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authorPeter Maydell <peter.maydell@linaro.org>2021-06-28 14:58:20 +0100
committerPeter Maydell <peter.maydell@linaro.org>2021-07-02 11:48:36 +0100
commitdfd66bc0f37dde37b8b2d7bad3a7075332e75fb4 (patch)
treee3c363f88c3b817a2574e750ee37a5e0dcd843a6 /target/arm/translate.h
parent303db86fc73c68d8774203d4796b9995cc122886 (diff)
target/arm: Make asimd_imm_const() public
The function asimd_imm_const() in translate-neon.c is an implementation of the pseudocode AdvSIMDExpandImm(), which we will also want for MVE. Move the implementation to translate.c, with a prototype in translate.h. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210628135835.6690-4-peter.maydell@linaro.org
Diffstat (limited to 'target/arm/translate.h')
-rw-r--r--target/arm/translate.h16
1 files changed, 16 insertions, 0 deletions
diff --git a/target/arm/translate.h b/target/arm/translate.h
index 99c917c571..6c8d5f6ede 100644
--- a/target/arm/translate.h
+++ b/target/arm/translate.h
@@ -532,4 +532,20 @@ static inline MemOp finalize_memop(DisasContext *s, MemOp opc)
return opc | s->be_data;
}
+/**
+ * asimd_imm_const: Expand an encoded SIMD constant value
+ *
+ * Expand a SIMD constant value. This is essentially the pseudocode
+ * AdvSIMDExpandImm, except that we also perform the boolean NOT needed for
+ * VMVN and VBIC (when cmode < 14 && op == 1).
+ *
+ * The combination cmode == 15 op == 1 is a reserved encoding for AArch32;
+ * callers must catch this.
+ *
+ * cmode = 2,3,4,5,6,7,10,11,12,13 imm=0 was UNPREDICTABLE in v7A but
+ * is either not unpredictable or merely CONSTRAINED UNPREDICTABLE in v8A;
+ * we produce an immediate constant value of 0 in these cases.
+ */
+uint64_t asimd_imm_const(uint32_t imm, int cmode, int op);
+
#endif /* TARGET_ARM_TRANSLATE_H */