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authorRichard Henderson <richard.henderson@linaro.org>2021-04-19 13:22:36 -0700
committerPeter Maydell <peter.maydell@linaro.org>2021-04-30 11:16:50 +0100
commit4479ec30c9c4d2399b6e5bf4e77d136cfd27aebd (patch)
treef4c8888291f69d3bbeeb17887498b85ab56dcf28 /target/arm/translate.h
parenteee81d41ec4c5bf9bbde4e4d35648e29e2244f3f (diff)
target/arm: Add ALIGN_MEM to TBFLAG_ANY
Use this to signal when memory access alignment is required. This value comes from the CCR register for M-profile, and from the SCTLR register for A-profile. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210419202257.161730-11-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/translate.h')
-rw-r--r--target/arm/translate.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/target/arm/translate.h b/target/arm/translate.h
index 50c2aba066..b185c14a03 100644
--- a/target/arm/translate.h
+++ b/target/arm/translate.h
@@ -87,6 +87,8 @@ typedef struct DisasContext {
bool bt;
/* True if any CP15 access is trapped by HSTR_EL2 */
bool hstr_active;
+ /* True if memory operations require alignment */
+ bool align_mem;
/*
* >= 0, a copy of PSTATE.BTYPE, which will be 0 without v8.5-BTI.
* < 0, set by the current instruction.