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| author | Richard Henderson <richard.henderson@linaro.org> | 2022-06-20 10:52:03 -0700 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2022-06-27 11:18:17 +0100 |
| commit | 5d7953adcfb30196ba684d3af69271528630367f (patch) | |
| tree | aaca7c487f23e2990a7ef3441769ad7da25a170f /target/arm/translate.h | |
| parent | 6ca54aa9a882ece5a6bcf5879f25bdcd7a95331f (diff) | |
target/arm: Add SVL to TB flags
We need SVL separate from VL for RDSVL et al, as well as
ZA storage loads and stores, which do not require PSTATE.SM.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220620175235.60881-20-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/translate.h')
| -rw-r--r-- | target/arm/translate.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/target/arm/translate.h b/target/arm/translate.h index 93766649f7..22fd882368 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -44,6 +44,7 @@ typedef struct DisasContext { int sve_excp_el; /* SVE exception EL or 0 if enabled */ int sme_excp_el; /* SME exception EL or 0 if enabled */ int vl; /* current vector length in bytes */ + int svl; /* current streaming vector length in bytes */ bool vfp_enabled; /* FP enabled via FPSCR.EN */ int vec_len; int vec_stride; |