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| author | Richard Henderson <richard.henderson@linaro.org> | 2020-06-25 20:31:17 -0700 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2020-06-26 14:31:12 +0100 |
| commit | 5f716a82388eb09754dd900e7dbb8ffa15897a28 (patch) | |
| tree | ba706c470d31b617765ec30d3b5e421cb2cd7887 /target/arm/translate.h | |
| parent | e26d0d226892f67435cadcce86df0ddfb9943174 (diff) | |
target/arm: Implement the LDGM, STGM, STZGM instructions
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200626033144.790098-20-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/translate.h')
| -rw-r--r-- | target/arm/translate.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/target/arm/translate.h b/target/arm/translate.h index 98bcc37c47..16f2699ad7 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -91,6 +91,8 @@ typedef struct DisasContext { * < 0, set by the current instruction. */ int8_t btype; + /* A copy of cpu->dcz_blocksize. */ + uint8_t dcz_blocksize; /* True if this page is guarded. */ bool guarded_page; /* Bottom two bits of XScale c15_cpar coprocessor access control reg */ |