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| author | Richard Henderson <richard.henderson@linaro.org> | 2018-10-24 07:50:19 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2018-10-24 07:51:37 +0100 |
| commit | 41f6c113c9ebf475554b2546c3e4c175db02c569 (patch) | |
| tree | e6ce9315625115e6e84b4f6a997260c88ad772f1 /target/arm/translate.h | |
| parent | 1dc8425e551be1371d657e94367f37130cd7aede (diff) | |
target/arm: Use gvec for VSRA
Move ssra_op and usra_op expanders from translate-a64.c.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20181011205206.3552-14-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/translate.h')
| -rw-r--r-- | target/arm/translate.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/target/arm/translate.h b/target/arm/translate.h index dea59c7214..5e13571b36 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -196,6 +196,8 @@ static inline TCGv_i32 get_ahp_flag(void) extern const GVecGen3 bsl_op; extern const GVecGen3 bit_op; extern const GVecGen3 bif_op; +extern const GVecGen2i ssra_op[4]; +extern const GVecGen2i usra_op[4]; /* * Forward to the isar_feature_* tests given a DisasContext pointer. |