diff options
| author | Peter Maydell <peter.maydell@linaro.org> | 2019-04-29 17:36:03 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2019-04-29 17:36:03 +0100 |
| commit | 019076b036da4444494de38388218040d9d3a26c (patch) | |
| tree | d44ec3f0c51f8be7742a50c42091630c9f74238c /target/arm/translate.c | |
| parent | e33cf0f8d8c9998a7616684f9d6aa0d181b88803 (diff) | |
target/arm: Implement VLSTM for v7M CPUs with an FPU
Implement the VLSTM instruction for v7M for the FPU present case.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20190416125744.27770-25-peter.maydell@linaro.org
Diffstat (limited to 'target/arm/translate.c')
| -rw-r--r-- | target/arm/translate.c | 15 |
1 files changed, 14 insertions, 1 deletions
diff --git a/target/arm/translate.c b/target/arm/translate.c index 4f29d09a28..99b38dd5f2 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -11818,7 +11818,20 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) if (!s->v8m_secure || (insn & 0x0040f0ff)) { goto illegal_op; } - /* Just NOP since FP support is not implemented */ + + if (arm_dc_feature(s, ARM_FEATURE_VFP)) { + TCGv_i32 fptr = load_reg(s, rn); + + if (extract32(insn, 20, 1)) { + /* VLLDM */ + } else { + gen_helper_v7m_vlstm(cpu_env, fptr); + } + tcg_temp_free_i32(fptr); + + /* End the TB, because we have updated FP control bits */ + s->base.is_jmp = DISAS_UPDATE; + } break; } if (arm_dc_feature(s, ARM_FEATURE_VFP) && |