diff options
| author | Lluís Vilanova <vilanova@ac.upc.edu> | 2017-07-14 11:17:35 +0300 |
|---|---|---|
| committer | Richard Henderson <rth@twiddle.net> | 2017-07-19 14:45:16 -0700 |
| commit | 9c489ea6bed134fecfd556b439c68bba48fbe102 (patch) | |
| tree | 3d54a182709bc45c16e276cc33e36f01cbe7f4ee /target/arm/translate.c | |
| parent | 797ed66d29909e9564b146a4a181005fc8096c69 (diff) | |
tcg: Pass generic CPUState to gen_intermediate_code()
Needed to implement a target-agnostic gen_intermediate_code()
in the future.
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Reviewed-by: Alex Benneé <alex.benee@linaro.org>
Reviewed-by: Emilio G. Cota <cota@braap.org>
Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu>
Message-Id: <150002025498.22386.18051908483085660588.stgit@frigg.lan>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Diffstat (limited to 'target/arm/translate.c')
| -rw-r--r-- | target/arm/translate.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/target/arm/translate.c b/target/arm/translate.c index d3003ae0d8..d1a5f56998 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -11795,10 +11795,10 @@ static bool insn_crosses_page(CPUARMState *env, DisasContext *s) } /* generate intermediate code for basic block 'tb'. */ -void gen_intermediate_code(CPUARMState *env, TranslationBlock *tb) +void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) { + CPUARMState *env = cs->env_ptr; ARMCPU *cpu = arm_env_get_cpu(env); - CPUState *cs = CPU(cpu); DisasContext dc1, *dc = &dc1; target_ulong pc_start; target_ulong next_page_start; @@ -11812,7 +11812,7 @@ void gen_intermediate_code(CPUARMState *env, TranslationBlock *tb) * the A32/T32 complexity to do with conditional execution/IT blocks/etc. */ if (ARM_TBFLAG_AARCH64_STATE(tb->flags)) { - gen_intermediate_code_a64(cpu, tb); + gen_intermediate_code_a64(cs, tb); return; } |