diff options
author | Richard Henderson <richard.henderson@linaro.org> | 2019-09-04 12:30:39 -0700 |
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committer | Peter Maydell <peter.maydell@linaro.org> | 2019-09-05 13:23:03 +0100 |
commit | 1cb1323433dca657a42483b2291c1ae923a91726 (patch) | |
tree | e65b8070baf89d27e90f2ad0e4e84bed8bc5d25a /target/arm/translate.c | |
parent | 07afd747f9fdd79fabf3a51416c7d795f873d297 (diff) |
target/arm: Convert T16 add pc/sp (immediate)
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20190904193059.26202-50-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/translate.c')
-rw-r--r-- | target/arm/translate.c | 12 |
1 files changed, 1 insertions, 11 deletions
diff --git a/target/arm/translate.c b/target/arm/translate.c index 4ae73d1c92..d8a4c7bf99 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10868,19 +10868,9 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn) case 7: /* load/store byte immediate offset, in decodetree */ case 8: /* load/store halfword immediate offset, in decodetree */ case 9: /* load/store from stack, in decodetree */ + case 10: /* add PC/SP (immediate), in decodetree */ goto illegal_op; - case 10: - /* - * 0b1010_xxxx_xxxx_xxxx - * - Add PC/SP (immediate) - */ - rd = (insn >> 8) & 7; - val = (insn & 0xff) * 4; - tmp = add_reg_for_lit(s, insn & (1 << 11) ? 13 : 15, val); - store_reg(s, rd, tmp); - break; - case 11: /* misc */ op = (insn >> 8) & 0xf; |