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| author | Richard Henderson <richard.henderson@linaro.org> | 2020-11-02 16:52:12 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2020-11-02 16:52:12 +0000 |
| commit | 015ee81a4c06b644969f621fd9965cc6372b879e (patch) | |
| tree | c0d9ebec85f8ba68acdbf0759cc9a0cc5b985894 /target/arm/translate-vfp.c.inc | |
| parent | b149dea55cce97cb226683d06af61984a1c11e96 (diff) | |
target/arm: Introduce neon_full_reg_offset
This function makes it clear that we're talking about the whole
register, and not the 32-bit piece at index 0. This fixes a bug
when running on a big-endian host.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201030022618.785675-2-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/translate-vfp.c.inc')
| -rw-r--r-- | target/arm/translate-vfp.c.inc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc index a7ed9bc81b..368bae0a73 100644 --- a/target/arm/translate-vfp.c.inc +++ b/target/arm/translate-vfp.c.inc @@ -653,7 +653,7 @@ static bool trans_VDUP(DisasContext *s, arg_VDUP *a) } tmp = load_reg(s, a->rt); - tcg_gen_gvec_dup_i32(size, neon_reg_offset(a->vn, 0), + tcg_gen_gvec_dup_i32(size, neon_full_reg_offset(a->vn), vec_size, vec_size, tmp); tcg_temp_free_i32(tmp); |