diff options
| author | Richard Henderson <richard.henderson@linaro.org> | 2022-05-27 11:18:24 -0700 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2022-05-30 17:05:09 +0100 |
| commit | c437c59ba1842dc8488316412cb071d57d8231d8 (patch) | |
| tree | 5efb3589cea7e8ed61458b808eb3706bcabc49d4 /target/arm/translate-sve.c | |
| parent | fa4bd72cc19e7309038f656c91caf1f1d4a00cee (diff) | |
target/arm: Reject dup_i w/ shifted byte early
Remove the unparsed extraction in trans_DUP_i,
which is intended to reject an 8-bit shift of
an 8-bit constant for 8-bit element.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220527181907.189259-72-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/translate-sve.c')
| -rw-r--r-- | target/arm/translate-sve.c | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index c0781ecf60..14faef0564 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -403,6 +403,12 @@ const uint64_t pred_esz_masks[4] = { 0x1111111111111111ull, 0x0101010101010101ull }; +static bool trans_INVALID(DisasContext *s, arg_INVALID *a) +{ + unallocated_encoding(s); + return true; +} + /* *** SVE Logical - Unpredicated Group */ @@ -3246,13 +3252,9 @@ static bool trans_FDUP(DisasContext *s, arg_FDUP *a) static bool trans_DUP_i(DisasContext *s, arg_DUP_i *a) { - if (a->esz == 0 && extract32(s->insn, 13, 1)) { - return false; - } if (sve_access_check(s)) { unsigned vsz = vec_full_reg_size(s); int dofs = vec_full_reg_offset(s, a->rd); - tcg_gen_gvec_dup_imm(a->esz, dofs, vsz, vsz, a->imm); } return true; |