aboutsummaryrefslogtreecommitdiff
path: root/target/arm/translate-sve.c
diff options
context:
space:
mode:
authorRichard Henderson <richard.henderson@linaro.org>2022-05-27 11:18:40 -0700
committerPeter Maydell <peter.maydell@linaro.org>2022-05-30 17:05:10 +0100
commit9c99ef66770d03e077535cca64c7ac827de308fb (patch)
treea6e0c305fa214e5639c829aaa846646249ab28af /target/arm/translate-sve.c
parentbdd4ce0d0e4f1e767bb1fa0462d7a8542e1af04b (diff)
target/arm: Use TRANS_FEAT for FMUL_zzx
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220527181907.189259-88-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/translate-sve.c')
-rw-r--r--target/arm/translate-sve.c26
1 files changed, 7 insertions, 19 deletions
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index d596e7a027..29fcc8b014 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -3557,25 +3557,13 @@ TRANS_FEAT(FMLS_zzxz, aa64_sve, do_FMLA_zzxz, a, true)
*** SVE Floating Point Multiply Indexed Group
*/
-static bool trans_FMUL_zzx(DisasContext *s, arg_FMUL_zzx *a)
-{
- static gen_helper_gvec_3_ptr * const fns[3] = {
- gen_helper_gvec_fmul_idx_h,
- gen_helper_gvec_fmul_idx_s,
- gen_helper_gvec_fmul_idx_d,
- };
-
- if (sve_access_check(s)) {
- unsigned vsz = vec_full_reg_size(s);
- TCGv_ptr status = fpstatus_ptr(a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR);
- tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, a->rd),
- vec_full_reg_offset(s, a->rn),
- vec_full_reg_offset(s, a->rm),
- status, vsz, vsz, a->index, fns[a->esz - 1]);
- tcg_temp_free_ptr(status);
- }
- return true;
-}
+static gen_helper_gvec_3_ptr * const fmul_idx_fns[4] = {
+ NULL, gen_helper_gvec_fmul_idx_h,
+ gen_helper_gvec_fmul_idx_s, gen_helper_gvec_fmul_idx_d,
+};
+TRANS_FEAT(FMUL_zzx, aa64_sve, gen_gvec_fpst_zzz,
+ fmul_idx_fns[a->esz], a->rd, a->rn, a->rm, a->index,
+ a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR)
/*
*** SVE Floating Point Fast Reduction Group