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| author | Peter Maydell <peter.maydell@linaro.org> | 2021-09-01 09:02:39 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2021-09-01 11:08:17 +0100 |
| commit | 98e40fbd792e13e98abd7f3d17f18a24edea4984 (patch) | |
| tree | a7db755e10a3e793958bd9ba322555b852474633 /target/arm/translate-mve.c | |
| parent | 73d260db3c7597c1efe7541057469358d2e5d001 (diff) | |
target/arm: Implement MVE VRINT insns
Implement the MVE VRINT insns, which round floating point inputs
to integer values, leaving them in floating point format.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'target/arm/translate-mve.c')
| -rw-r--r-- | target/arm/translate-mve.c | 45 |
1 files changed, 45 insertions, 0 deletions
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c index 194ef99cc7..2ed91577ec 100644 --- a/target/arm/translate-mve.c +++ b/target/arm/translate-mve.c @@ -641,6 +641,51 @@ DO_VCVT_SH(VCVTT_SH, vcvtt_sh) DO_VCVT_SH(VCVTB_HS, vcvtb_hs) DO_VCVT_SH(VCVTT_HS, vcvtt_hs) +#define DO_VRINT(INSN, RMODE) \ + static void gen_##INSN##h(TCGv_ptr env, TCGv_ptr qd, TCGv_ptr qm) \ + { \ + gen_helper_mve_vrint_rm_h(env, qd, qm, \ + tcg_constant_i32(arm_rmode_to_sf(RMODE))); \ + } \ + static void gen_##INSN##s(TCGv_ptr env, TCGv_ptr qd, TCGv_ptr qm) \ + { \ + gen_helper_mve_vrint_rm_s(env, qd, qm, \ + tcg_constant_i32(arm_rmode_to_sf(RMODE))); \ + } \ + static bool trans_##INSN(DisasContext *s, arg_1op *a) \ + { \ + static MVEGenOneOpFn * const fns[] = { \ + NULL, \ + gen_##INSN##h, \ + gen_##INSN##s, \ + NULL, \ + }; \ + if (!dc_isar_feature(aa32_mve_fp, s)) { \ + return false; \ + } \ + return do_1op(s, a, fns[a->size]); \ + } + +DO_VRINT(VRINTN, FPROUNDING_TIEEVEN) +DO_VRINT(VRINTA, FPROUNDING_TIEAWAY) +DO_VRINT(VRINTZ, FPROUNDING_ZERO) +DO_VRINT(VRINTM, FPROUNDING_NEGINF) +DO_VRINT(VRINTP, FPROUNDING_POSINF) + +static bool trans_VRINTX(DisasContext *s, arg_1op *a) +{ + static MVEGenOneOpFn * const fns[] = { + NULL, + gen_helper_mve_vrintx_h, + gen_helper_mve_vrintx_s, + NULL, + }; + if (!dc_isar_feature(aa32_mve_fp, s)) { + return false; + } + return do_1op(s, a, fns[a->size]); +} + /* Narrowing moves: only size 0 and 1 are valid */ #define DO_VMOVN(INSN, FN) \ static bool trans_##INSN(DisasContext *s, arg_1op *a) \ |