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| author | Peter Maydell <peter.maydell@linaro.org> | 2021-09-01 09:02:36 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2021-09-01 11:08:16 +0100 |
| commit | 90257a4f35efef15380f45339fecc348e762acc6 (patch) | |
| tree | 7bf62bfd7bd177af35c5cdebbf9331aa95a1f084 /target/arm/translate-mve.c | |
| parent | d3cd965c846bb350637090d2d11bc578b79f87cd (diff) | |
target/arm: Implement MVE VMAXNMA and VMINNMA
Implement the MVE VMAXNMA and VMINNMA insns; these are 2-operand, but
the destination register must be the same as one of the source
registers.
We defer the decode of the size in bit 28 to the individual insn
patterns rather than doing it in the format, because otherwise we
would have a single insn pattern that overlapped with two groups (eg
VMAXNMA with the VMULH_S and VMULH_U groups). Having two insn
patterns per insn seems clearer than a complex multilevel nesting
of overlapping and non-overlapping groups.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/translate-mve.c')
| -rw-r--r-- | target/arm/translate-mve.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c index d62ed1fc29..4d702da808 100644 --- a/target/arm/translate-mve.c +++ b/target/arm/translate-mve.c @@ -864,6 +864,8 @@ DO_2OP_FP(VCMLA0, vcmla0) DO_2OP_FP(VCMLA90, vcmla90) DO_2OP_FP(VCMLA180, vcmla180) DO_2OP_FP(VCMLA270, vcmla270) +DO_2OP_FP(VMAXNMA, vmaxnma) +DO_2OP_FP(VMINNMA, vminnma) static bool do_2op_scalar(DisasContext *s, arg_2scalar *a, MVEGenTwoOpScalarFn fn) |