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| author | Peter Maydell <peter.maydell@linaro.org> | 2021-09-01 09:02:39 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2021-09-01 11:08:17 +0100 |
| commit | 73d260db3c7597c1efe7541057469358d2e5d001 (patch) | |
| tree | f0d0963e04faf37341b71d4060afe7aa7b0f010a /target/arm/translate-mve.c | |
| parent | 53fc5f61394927101416dc618480967dc7cd2171 (diff) | |
target/arm: Implement MVE VCVT between single and half precision
Implement the MVE VCVT instruction which converts between single
and half precision floating point.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'target/arm/translate-mve.c')
| -rw-r--r-- | target/arm/translate-mve.c | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c index e80a55eb62..194ef99cc7 100644 --- a/target/arm/translate-mve.c +++ b/target/arm/translate-mve.c @@ -627,6 +627,20 @@ DO_VCVT_RMODE(VCVTPU, FPROUNDING_POSINF, true) DO_VCVT_RMODE(VCVTMS, FPROUNDING_NEGINF, false) DO_VCVT_RMODE(VCVTMU, FPROUNDING_NEGINF, true) +#define DO_VCVT_SH(INSN, FN) \ + static bool trans_##INSN(DisasContext *s, arg_1op *a) \ + { \ + if (!dc_isar_feature(aa32_mve_fp, s)) { \ + return false; \ + } \ + return do_1op(s, a, gen_helper_mve_##FN); \ + } \ + +DO_VCVT_SH(VCVTB_SH, vcvtb_sh) +DO_VCVT_SH(VCVTT_SH, vcvtt_sh) +DO_VCVT_SH(VCVTB_HS, vcvtb_hs) +DO_VCVT_SH(VCVTT_HS, vcvtt_hs) + /* Narrowing moves: only size 0 and 1 are valid */ #define DO_VMOVN(INSN, FN) \ static bool trans_##INSN(DisasContext *s, arg_1op *a) \ |