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authorRichard Henderson <richard.henderson@linaro.org>2021-04-16 11:31:06 -0700
committerPeter Maydell <peter.maydell@linaro.org>2021-04-30 11:16:49 +0100
commit33e74c3172defc841692b4281d2dbd8f8a966e17 (patch)
treeb753eeab1377b2af7a0c9d444d68549020622940 /target/arm/translate-a64.h
parent4c3310c73f7349f1aabae55a7babd6419eeb1d04 (diff)
target/arm: Remove log2_esize parameter to gen_mte_checkN
The log2_esize parameter is not used except trivially. Drop the parameter and the deferral to gen_mte_check1. This fixes a bug in that the parameters as documented in the header file were the reverse from those in the implementation. Which meant that translate-sve.c was passing the parameters in the wrong order. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210416183106.1516563-10-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/translate-a64.h')
-rw-r--r--target/arm/translate-a64.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/target/arm/translate-a64.h b/target/arm/translate-a64.h
index 3668b671dd..868d355048 100644
--- a/target/arm/translate-a64.h
+++ b/target/arm/translate-a64.h
@@ -44,7 +44,7 @@ TCGv_i64 clean_data_tbi(DisasContext *s, TCGv_i64 addr);
TCGv_i64 gen_mte_check1(DisasContext *s, TCGv_i64 addr, bool is_write,
bool tag_checked, int log2_size);
TCGv_i64 gen_mte_checkN(DisasContext *s, TCGv_i64 addr, bool is_write,
- bool tag_checked, int count, int log2_esize);
+ bool tag_checked, int size);
/* We should have at some point before trying to access an FP register
* done the necessary access check, so assert that