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authorRichard Henderson <richard.henderson@linaro.org>2020-06-25 20:31:21 -0700
committerPeter Maydell <peter.maydell@linaro.org>2020-06-26 14:31:12 +0100
commit0a405be2b8fd9506a009b10d7d2d98c394b36db6 (patch)
treebb36a1252700ba1ff18f4c4b77ac538a0e05730e /target/arm/translate-a64.h
parent38659d311d05e6c5feff6bddcc1c33b60d3b86a1 (diff)
target/arm: Add gen_mte_check1
Replace existing uses of check_data_tbi in translate-a64.c that perform a single logical memory access. Leave the helper blank for now to reduce the patch size. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200626033144.790098-24-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/translate-a64.h')
-rw-r--r--target/arm/translate-a64.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/target/arm/translate-a64.h b/target/arm/translate-a64.h
index da0f59a2ce..daab6a9666 100644
--- a/target/arm/translate-a64.h
+++ b/target/arm/translate-a64.h
@@ -40,6 +40,8 @@ TCGv_ptr get_fpstatus_ptr(bool);
bool logic_imm_decode_wmask(uint64_t *result, unsigned int immn,
unsigned int imms, unsigned int immr);
bool sve_access_check(DisasContext *s);
+TCGv_i64 gen_mte_check1(DisasContext *s, TCGv_i64 addr, bool is_write,
+ bool tag_checked, int log2_size);
/* We should have at some point before trying to access an FP register
* done the necessary access check, so assert that