diff options
| author | Tony Nguyen <tony.nguyen@bt.com> | 2019-08-24 04:10:58 +1000 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2019-09-03 08:30:38 -0700 |
| commit | 14776ab5a12972ea439c7fb2203a4c15a09094b4 (patch) | |
| tree | b53091625b410a722bf5f4e17a9631457994eed4 /target/arm/translate-a64.h | |
| parent | fec105c2abda8567ec15230429c41429b5ee307c (diff) | |
tcg: TCGMemOp is now accelerator independent MemOp
Preparation for collapsing the two byte swaps, adjust_endianness and
handle_bswap, along the I/O path.
Target dependant attributes are conditionalized upon NEED_CPU_H.
Signed-off-by: Tony Nguyen <tony.nguyen@bt.com>
Acked-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Acked-by: Cornelia Huck <cohuck@redhat.com>
Message-Id: <81d9cd7d7f5aaadfa772d6c48ecee834e9cf7882.1566466906.git.tony.nguyen@bt.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'target/arm/translate-a64.h')
| -rw-r--r-- | target/arm/translate-a64.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target/arm/translate-a64.h b/target/arm/translate-a64.h index 12ad8ac6ed..a0f4f535ba 100644 --- a/target/arm/translate-a64.h +++ b/target/arm/translate-a64.h @@ -62,7 +62,7 @@ static inline void assert_fp_access_checked(DisasContext *s) * the FP/vector register Qn. */ static inline int vec_reg_offset(DisasContext *s, int regno, - int element, TCGMemOp size) + int element, MemOp size) { int element_size = 1 << size; int offs = element * element_size; |