diff options
| author | Richard Henderson <richard.henderson@linaro.org> | 2022-04-26 09:30:12 -0700 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2022-04-28 13:35:58 +0100 |
| commit | 4cb05eb74c9137911aaac47e56ee62c6e3bc7991 (patch) | |
| tree | f2b4c0dba2235a1627989719d376faea8bb658b9 /target/arm/translate-a64.c | |
| parent | 728963ea97b65ccf19247f5d55968d4a65ddcd05 (diff) | |
target/arm: Use tcg_constant in disas_data_proc_2src
Existing temp usage treats t1 as both zero and as a
temporary. Rearrange to only require one temporary,
so remove t1 and rename t2.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20220426163043.100432-17-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/translate-a64.c')
| -rw-r--r-- | target/arm/translate-a64.c | 12 |
1 files changed, 5 insertions, 7 deletions
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index ff08306d2b..358f42026c 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -5734,15 +5734,13 @@ static void disas_data_proc_2src(DisasContext *s, uint32_t insn) if (sf == 0 || !dc_isar_feature(aa64_mte_insn_reg, s)) { goto do_unallocated; } else { - TCGv_i64 t1 = tcg_const_i64(1); - TCGv_i64 t2 = tcg_temp_new_i64(); + TCGv_i64 t = tcg_temp_new_i64(); - tcg_gen_extract_i64(t2, cpu_reg_sp(s, rn), 56, 4); - tcg_gen_shl_i64(t1, t1, t2); - tcg_gen_or_i64(cpu_reg(s, rd), cpu_reg(s, rm), t1); + tcg_gen_extract_i64(t, cpu_reg_sp(s, rn), 56, 4); + tcg_gen_shl_i64(t, tcg_constant_i64(1), t); + tcg_gen_or_i64(cpu_reg(s, rd), cpu_reg(s, rm), t); - tcg_temp_free_i64(t1); - tcg_temp_free_i64(t2); + tcg_temp_free_i64(t); } break; case 8: /* LSLV */ |