diff options
| author | Richard Henderson <richard.henderson@linaro.org> | 2024-05-24 16:20:50 -0700 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2024-05-28 14:29:01 +0100 |
| commit | f240df3c31b40e4cf1af1f156a88efc1a1df406c (patch) | |
| tree | cdd1fdb238c97aa93a19f5b2bc40e54951ef8470 /target/arm/tcg/a64.decode | |
| parent | 641d8231426f02ab814c9bf97fcacea076cb3ef1 (diff) | |
target/arm: Convert disas_simd_3same_logic to decodetree
This includes AND, ORR, EOR, BIC, ORN, BSF, BIT, BIF.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240524232121.284515-37-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/tcg/a64.decode')
| -rw-r--r-- | target/arm/tcg/a64.decode | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index 7e993ed345..f48adef5bb 100644 --- a/target/arm/tcg/a64.decode +++ b/target/arm/tcg/a64.decode @@ -55,6 +55,7 @@ @rrr_q1e3 ........ ... rm:5 ...... rn:5 rd:5 &qrrr_e q=1 esz=3 @rrrr_q1e3 ........ ... rm:5 . ra:5 rn:5 rd:5 &qrrrr_e q=1 esz=3 +@qrrr_b . q:1 ...... ... rm:5 ...... rn:5 rd:5 &qrrr_e esz=0 @qrrr_h . q:1 ...... ... rm:5 ...... rn:5 rd:5 &qrrr_e esz=1 @qrrr_sd . q:1 ...... ... rm:5 ...... rn:5 rd:5 &qrrr_e esz=%esz_sd @qrrr_e . q:1 ...... esz:2 . rm:5 ...... rn:5 rd:5 &qrrr_e @@ -847,6 +848,15 @@ SMINP_v 0.00 1110 ..1 ..... 10101 1 ..... ..... @qrrr_e UMAXP_v 0.10 1110 ..1 ..... 10100 1 ..... ..... @qrrr_e UMINP_v 0.10 1110 ..1 ..... 10101 1 ..... ..... @qrrr_e +AND_v 0.00 1110 001 ..... 00011 1 ..... ..... @qrrr_b +BIC_v 0.00 1110 011 ..... 00011 1 ..... ..... @qrrr_b +ORR_v 0.00 1110 101 ..... 00011 1 ..... ..... @qrrr_b +ORN_v 0.00 1110 111 ..... 00011 1 ..... ..... @qrrr_b +EOR_v 0.10 1110 001 ..... 00011 1 ..... ..... @qrrr_b +BSL_v 0.10 1110 011 ..... 00011 1 ..... ..... @qrrr_b +BIT_v 0.10 1110 101 ..... 00011 1 ..... ..... @qrrr_b +BIF_v 0.10 1110 111 ..... 00011 1 ..... ..... @qrrr_b + ### Advanced SIMD scalar x indexed element FMUL_si 0101 1111 00 .. .... 1001 . 0 ..... ..... @rrx_h |