diff options
| author | Peter Maydell <peter.maydell@linaro.org> | 2020-08-03 12:18:48 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2020-08-24 10:15:08 +0100 |
| commit | 4c498dcfd84281f20bd55072630027d1b3c115fd (patch) | |
| tree | 72ea9c8100a6c4070fd343db2dc0ee90a24fecfd /target/arm/t32.decode | |
| parent | a3494d4671797c291c88bd414acb0aead15f7239 (diff) | |
target/arm: Convert T32 coprocessor insns to decodetree
Convert the T32 coprocessor instructions to decodetree.
As with the A32 conversion, this corrects an underdecoding
where we did not check that MRRC/MCRR [24:21] were 0b0010
and so treated some kinds of LDC/STC and MRRC/MCRR rather
than UNDEFing them.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200803111849.13368-7-peter.maydell@linaro.org
Diffstat (limited to 'target/arm/t32.decode')
| -rw-r--r-- | target/arm/t32.decode | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/target/arm/t32.decode b/target/arm/t32.decode index c21a988f97..7069d821fd 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -45,6 +45,8 @@ &sat !extern rd rn satimm imm sh &pkh !extern rd rn rm imm tb &cps !extern mode imod M A I F +&mcr !extern cp opc1 crn crm opc2 rt +&mcrr !extern cp opc1 crm rt rt2 # Data-processing (register) @@ -621,6 +623,23 @@ RFE 1110 1001 10.1 .... 1100000000000000 @rfe pu=1 SRS 1110 1000 00.0 1101 1100 0000 000. .... @srs pu=2 SRS 1110 1001 10.0 1101 1100 0000 000. .... @srs pu=1 +# Coprocessor instructions + +# We decode MCR, MCR, MRRC and MCRR only, because for QEMU the +# other coprocessor instructions always UNDEF. +# The trans_ functions for these will ignore cp values 8..13 for v7 or +# earlier, and 0..13 for v8 and later, because those areas of the +# encoding space may be used for other things, such as VFP or Neon. + +@mcr .... .... opc1:3 . crn:4 rt:4 cp:4 opc2:3 . crm:4 +@mcrr .... .... .... rt2:4 rt:4 cp:4 opc1:4 crm:4 + +MCRR 1110 1100 0100 .... .... .... .... .... @mcrr +MRRC 1110 1100 0101 .... .... .... .... .... @mcrr + +MCR 1110 1110 ... 0 .... .... .... ... 1 .... @mcr +MRC 1110 1110 ... 1 .... .... .... ... 1 .... @mcr + # Branches %imm24 26:s1 13:1 11:1 16:10 0:11 !function=t32_branch24 |