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authorRichard Henderson <richard.henderson@linaro.org>2019-09-04 12:30:26 -0700
committerPeter Maydell <peter.maydell@linaro.org>2019-09-05 13:23:03 +0100
commit52f83b9c68bdde8d3da5f49292d3561bd474651d (patch)
tree2e24e54d3fb9e631f4c32f4ca31d8fa9eef8d9bb /target/arm/t32.decode
parent519b84711ea36bb8a339096e207b6b9b65cd2051 (diff)
target/arm: Convert CPS (privileged)
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190904193059.26202-37-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/t32.decode')
-rw-r--r--target/arm/t32.decode5
1 files changed, 5 insertions, 0 deletions
diff --git a/target/arm/t32.decode b/target/arm/t32.decode
index 63bca82575..11a9a2ef58 100644
--- a/target/arm/t32.decode
+++ b/target/arm/t32.decode
@@ -44,6 +44,7 @@
&bfi !extern rd rn lsb msb
&sat !extern rd rn satimm imm sh
&pkh !extern rd rn rm imm tb
+&cps !extern mode imod M A I F
# Data-processing (register)
@@ -306,6 +307,10 @@ CLZ 1111 1010 1011 ---- 1111 .... 1000 .... @rdm
NOP 1111 0011 1010 1111 1000 0000 ---- ----
}
+ # If imod == '00' && M == '0' then SEE "Hint instructions", above.
+ CPS 1111 0011 1010 1111 1000 0 imod:2 M:1 A:1 I:1 F:1 mode:5 \
+ &cps
+
# Miscellaneous control
{
CLREX 1111 0011 1011 1111 1000 1111 0010 1111