diff options
| author | Richard Henderson <richard.henderson@linaro.org> | 2019-09-04 12:30:54 -0700 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2019-09-05 13:23:04 +0100 |
| commit | 151c2f2841b01bf6fef079c9f1db15a86cae8276 (patch) | |
| tree | 9d5f83d3e40559d88eeee974f4dc0343056064f8 /target/arm/t16.decode | |
| parent | 43f7e42c7d515f41ff243034f51b28267ae69938 (diff) | |
target/arm: Convert T16, shift immediate
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20190904193059.26202-65-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/t16.decode')
| -rw-r--r-- | target/arm/t16.decode | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/target/arm/t16.decode b/target/arm/t16.decode index f128110dee..79a1d66d6c 100644 --- a/target/arm/t16.decode +++ b/target/arm/t16.decode @@ -126,6 +126,14 @@ ADD_rri 10101 rd:3 ........ \ STM 11000 ... ........ @ldstm LDM_t16 11001 ... ........ @ldstm +# Shift (immediate) + +@shift_i ..... shim:5 rm:3 rd:3 &s_rrr_shi %s rn=%reg_0 + +MOV_rxri 000 00 ..... ... ... @shift_i shty=0 # LSL +MOV_rxri 000 01 ..... ... ... @shift_i shty=1 # LSR +MOV_rxri 000 10 ..... ... ... @shift_i shty=2 # ASR + # Add/subtract (three low registers) @addsub_3 ....... rm:3 rn:3 rd:3 \ |