diff options
| author | Richard Henderson <richard.henderson@linaro.org> | 2019-09-04 12:30:47 -0700 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2019-09-05 13:23:04 +0100 |
| commit | 20556e7bd6111266fbf1d81e4ff7a89bfa5795a7 (patch) | |
| tree | a6d5d50bb399f1ac30958382417c435cccc946dd /target/arm/t16.decode | |
| parent | e6f69612cc79e2acc05dafda8695f791a916946f (diff) | |
target/arm: Convert T16, Change processor state
Add a check for ARMv6 in trans_CPS. We had this correct in
the T16 path, but had previously forgotten the check on the
A32 and T32 paths.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20190904193059.26202-58-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/t16.decode')
| -rw-r--r-- | target/arm/t16.decode | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/target/arm/t16.decode b/target/arm/t16.decode index b5b5086e8a..032902a1f4 100644 --- a/target/arm/t16.decode +++ b/target/arm/t16.decode @@ -29,6 +29,8 @@ &ldst_rr !extern p w u rn rt rm shimm shtype &ldst_ri !extern p w u rn rt imm &ldst_block !extern rn i b u w list +&setend !extern E +&cps !extern mode imod M A I F # Set S if the instruction is outside of an IT block. %s !function=t16_setflags @@ -183,3 +185,13 @@ SXTAH 1011 0010 00 ... ... @extend SXTAB 1011 0010 01 ... ... @extend UXTAH 1011 0010 10 ... ... @extend UXTAB 1011 0010 11 ... ... @extend + +# Change processor state + +%imod 4:1 !function=plus_2 + +SETEND 1011 0110 010 1 E:1 000 &setend +{ + CPS 1011 0110 011 . 0 A:1 I:1 F:1 &cps mode=0 M=0 %imod + CPS_v7m 1011 0110 011 im:1 00 I:1 F:1 +} |