diff options
| author | Richard Henderson <richard.henderson@linaro.org> | 2019-09-04 12:30:41 -0700 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2019-09-05 13:23:04 +0100 |
| commit | c4d3095bb62bdac0b4f9cb180bd7aa0b40c2c270 (patch) | |
| tree | c9b387cd734a5ba310c2909ed8b1c5ac590ea4db /target/arm/t16.decode | |
| parent | 6e8514ba408f3cc758cd47e2da5475d8684507ec (diff) | |
target/arm: Convert T16 add/sub (3 low, 2 low and imm)
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20190904193059.26202-52-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/t16.decode')
| -rw-r--r-- | target/arm/t16.decode | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/target/arm/t16.decode b/target/arm/t16.decode index a7a437f930..2b5f368d31 100644 --- a/target/arm/t16.decode +++ b/target/arm/t16.decode @@ -117,3 +117,19 @@ ADD_rri 10101 rd:3 ........ \ STM 11000 ... ........ @ldstm LDM_t16 11001 ... ........ @ldstm + +# Add/subtract (three low registers) + +@addsub_3 ....... rm:3 rn:3 rd:3 \ + &s_rrr_shi %s shim=0 shty=0 + +ADD_rrri 0001100 ... ... ... @addsub_3 +SUB_rrri 0001101 ... ... ... @addsub_3 + +# Add/subtract (two low registers and immediate) + +@addsub_2i ....... imm:3 rn:3 rd:3 \ + &s_rri_rot %s rot=0 + +ADD_rri 0001 110 ... ... ... @addsub_2i +SUB_rri 0001 111 ... ... ... @addsub_2i |