diff options
| author | Richard Henderson <richard.henderson@linaro.org> | 2022-07-08 20:45:23 +0530 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2022-07-11 13:43:51 +0100 |
| commit | 598ab0b24c0cb807b3f380ab422915dd6c229026 (patch) | |
| tree | 889b79e53e7b025dc230477adf3a8157d7d77cfd /target/arm/sve.decode | |
| parent | 23a5e3859f55c11018f046957dbbbbbbbba39b28 (diff) | |
target/arm: Implement PSEL
This is an SVE instruction that operates using the SVE vector
length but that it is present only if SME is implemented.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220708151540.18136-29-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/sve.decode')
| -rw-r--r-- | target/arm/sve.decode | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/target/arm/sve.decode b/target/arm/sve.decode index 95af08c139..966803cbb7 100644 --- a/target/arm/sve.decode +++ b/target/arm/sve.decode @@ -1674,3 +1674,23 @@ BFMLALT_zzxw 01100100 11 1 ..... 0100.1 ..... ..... @rrxr_3a esz=2 ### SVE2 floating-point bfloat16 dot-product (indexed) BFDOT_zzxz 01100100 01 1 ..... 010000 ..... ..... @rrxr_2 esz=2 + +### SVE broadcast predicate element + +&psel esz pd pn pm rv imm +%psel_rv 16:2 !function=plus_12 +%psel_imm_b 22:2 19:2 +%psel_imm_h 22:2 20:1 +%psel_imm_s 22:2 +%psel_imm_d 23:1 +@psel ........ .. . ... .. .. pn:4 . pm:4 . pd:4 \ + &psel rv=%psel_rv + +PSEL 00100101 .. 1 ..1 .. 01 .... 0 .... 0 .... \ + @psel esz=0 imm=%psel_imm_b +PSEL 00100101 .. 1 .10 .. 01 .... 0 .... 0 .... \ + @psel esz=1 imm=%psel_imm_h +PSEL 00100101 .. 1 100 .. 01 .... 0 .... 0 .... \ + @psel esz=2 imm=%psel_imm_s +PSEL 00100101 .1 1 000 .. 01 .... 0 .... 0 .... \ + @psel esz=3 imm=%psel_imm_d |