diff options
| author | Richard Henderson <richard.henderson@linaro.org> | 2018-05-18 17:48:09 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2018-05-18 17:48:09 +0100 |
| commit | 0762cd428fd7b471207f5cb5b4bd4bd8f141dbe0 (patch) | |
| tree | a06e24d194bce60143b881150073aa3623cf5f85 /target/arm/sve.decode | |
| parent | 4b242d9c1b6beaf5c81d84e956243b614a4a1d84 (diff) | |
target/arm: Implement SVE floating-point exponential accelerator
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180516223007.10256-21-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/sve.decode')
| -rw-r--r-- | target/arm/sve.decode | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/target/arm/sve.decode b/target/arm/sve.decode index 691876de4e..cd53b95831 100644 --- a/target/arm/sve.decode +++ b/target/arm/sve.decode @@ -66,6 +66,7 @@ # Two operand @pd_pn ........ esz:2 .. .... ....... rn:4 . rd:4 &rr_esz +@rd_rn ........ esz:2 ...... ...... rn:5 rd:5 &rr_esz # Three operand with unused vector element size @rd_rn_rm_e0 ........ ... rm:5 ... ... rn:5 rd:5 &rrr_esz esz=0 @@ -288,6 +289,12 @@ ADR_u32 00000100 01 1 ..... 1010 .. ..... ..... @rd_rn_msz_rm ADR_p32 00000100 10 1 ..... 1010 .. ..... ..... @rd_rn_msz_rm ADR_p64 00000100 11 1 ..... 1010 .. ..... ..... @rd_rn_msz_rm +### SVE Integer Misc - Unpredicated Group + +# SVE floating-point exponential accelerator +# Note esz != 0 +FEXPA 00000100 .. 1 00000 101110 ..... ..... @rd_rn + ### SVE Predicate Logical Operations Group # SVE predicate logical operations |