diff options
| author | Richard Henderson <richard.henderson@linaro.org> | 2018-06-29 15:11:12 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2018-06-29 15:11:12 +0100 |
| commit | 18fc24057815bf3d956cfab892a2bc2344bd1dcb (patch) | |
| tree | 5e3a9b96be293cf5c8f12d27a7ad32597e57411d /target/arm/sve.decode | |
| parent | 2cc99919a81a62589a4a6b0f365eabfead1db1a7 (diff) | |
target/arm: Implement SVE fp complex multiply add (indexed)
Enhance the existing helpers to support SVE, which takes the
index from each 128-bit segment. The change has no effect
for AdvSIMD, since there is only one such segment.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 20180627043328.11531-32-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/sve.decode')
| -rw-r--r-- | target/arm/sve.decode | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/target/arm/sve.decode b/target/arm/sve.decode index e342cfdf14..62365ed90f 100644 --- a/target/arm/sve.decode +++ b/target/arm/sve.decode @@ -733,6 +733,12 @@ FCADD 01100100 esz:2 00000 rot:1 100 pg:3 rm:5 rd:5 \ FCMLA_zpzzz 01100100 esz:2 0 rm:5 0 rot:2 pg:3 rn:5 rd:5 \ ra=%reg_movprfx +# SVE floating-point complex multiply-add (indexed) +FCMLA_zzxz 01100100 10 1 index:2 rm:3 0001 rot:2 rn:5 rd:5 \ + ra=%reg_movprfx esz=1 +FCMLA_zzxz 01100100 11 1 index:1 rm:4 0001 rot:2 rn:5 rd:5 \ + ra=%reg_movprfx esz=2 + ### SVE FP Multiply-Add Indexed Group # SVE floating-point multiply-add (indexed) |