diff options
| author | Richard Henderson <richard.henderson@linaro.org> | 2018-06-15 14:57:15 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2018-06-15 15:23:34 +0100 |
| commit | d3fe4a29d754dee73cbf3cb7584db222981179ac (patch) | |
| tree | 7c67a9647581e64f1b08a6fd96709da99cb7d1ba /target/arm/sve.decode | |
| parent | b48ff24098c72f86e187e6abb7e9ca4de40a7fb4 (diff) | |
target/arm: Implement SVE Select Vectors Group
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180613015641.5667-11-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/sve.decode')
| -rw-r--r-- | target/arm/sve.decode | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/target/arm/sve.decode b/target/arm/sve.decode index a9fa631252..91522d8e13 100644 --- a/target/arm/sve.decode +++ b/target/arm/sve.decode @@ -98,6 +98,7 @@ &rprr_esz rn=%reg_movprfx @rdm_pg_rn ........ esz:2 ... ... ... pg:3 rn:5 rd:5 \ &rprr_esz rm=%reg_movprfx +@rd_pg4_rn_rm ........ esz:2 . rm:5 .. pg:4 rn:5 rd:5 &rprr_esz # Three register operand, with governing predicate, vector element size @rda_pg_rn_rm ........ esz:2 . rm:5 ... pg:3 rn:5 rd:5 \ @@ -466,6 +467,11 @@ RBIT 00000101 .. 1001 11 100 ... ..... ..... @rd_pg_rn # SVE vector splice (predicated) SPLICE 00000101 .. 101 100 100 ... ..... ..... @rdn_pg_rm +### SVE Select Vectors Group + +# SVE select vector elements (predicated) +SEL_zpzz 00000101 .. 1 ..... 11 .... ..... ..... @rd_pg4_rn_rm + ### SVE Predicate Logical Operations Group # SVE predicate logical operations |