diff options
| author | Richard Henderson <richard.henderson@linaro.org> | 2018-06-29 15:11:08 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2018-06-29 15:11:08 +0100 |
| commit | 23fbe79faa38cb4acc59f956a63feba3c2cc73ac (patch) | |
| tree | 1d353101e149450d08aee0614ba675f1378d9539 /target/arm/sve.decode | |
| parent | ca40a6e6e390eb1cad7ade881dc7c622793f9324 (diff) | |
target/arm: Implement SVE FP Fast Reduction Group
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180627043328.11531-20-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/sve.decode')
| -rw-r--r-- | target/arm/sve.decode | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/target/arm/sve.decode b/target/arm/sve.decode index 15fa790d5b..66b0fd0cc4 100644 --- a/target/arm/sve.decode +++ b/target/arm/sve.decode @@ -735,6 +735,14 @@ FMUL_zzx 01100100 0.1 .. rm:3 001000 rn:5 rd:5 \ FMUL_zzx 01100100 101 index:2 rm:3 001000 rn:5 rd:5 esz=2 FMUL_zzx 01100100 111 index:1 rm:4 001000 rn:5 rd:5 esz=3 +### SVE FP Fast Reduction Group + +FADDV 01100101 .. 000 000 001 ... ..... ..... @rd_pg_rn +FMAXNMV 01100101 .. 000 100 001 ... ..... ..... @rd_pg_rn +FMINNMV 01100101 .. 000 101 001 ... ..... ..... @rd_pg_rn +FMAXV 01100101 .. 000 110 001 ... ..... ..... @rd_pg_rn +FMINV 01100101 .. 000 111 001 ... ..... ..... @rd_pg_rn + ### SVE FP Accumulating Reduction Group # SVE floating-point serial reduction (predicated) |