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authorRichard Henderson <richard.henderson@linaro.org>2018-06-29 15:11:09 +0100
committerPeter Maydell <peter.maydell@linaro.org>2018-06-29 15:11:09 +0100
commit4d2e2a03384a43c641e0cbca7ac79d7d0c50f666 (patch)
treec0a271bbb68b36f06f70c3699e9a206d6c682670 /target/arm/sve.decode
parent3887c0388d39930ab419d4ae6e8ca5ea67a74ad5 (diff)
target/arm: Implement SVE FP Compare with Zero Group
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180627043328.11531-22-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/sve.decode')
-rw-r--r--target/arm/sve.decode10
1 files changed, 10 insertions, 0 deletions
diff --git a/target/arm/sve.decode b/target/arm/sve.decode
index ca93bdb2b3..a774becd6c 100644
--- a/target/arm/sve.decode
+++ b/target/arm/sve.decode
@@ -140,6 +140,7 @@
# One register operand, with governing predicate, vector element size
@rd_pg_rn ........ esz:2 ... ... ... pg:3 rn:5 rd:5 &rpr_esz
@rd_pg4_pn ........ esz:2 ... ... .. pg:4 . rn:4 rd:5 &rpr_esz
+@pd_pg_rn ........ esz:2 ... ... ... pg:3 rn:5 . rd:4 &rpr_esz
# One register operand, with governing predicate, no vector element size
@rd_pg_rn_e0 ........ .. ... ... ... pg:3 rn:5 rd:5 &rpr_esz esz=0
@@ -748,6 +749,15 @@ FMINV 01100101 .. 000 111 001 ... ..... ..... @rd_pg_rn
FRECPE 01100101 .. 001 110 001100 ..... ..... @rd_rn
FRSQRTE 01100101 .. 001 111 001100 ..... ..... @rd_rn
+### SVE FP Compare with Zero Group
+
+FCMGE_ppz0 01100101 .. 0100 00 001 ... ..... 0 .... @pd_pg_rn
+FCMGT_ppz0 01100101 .. 0100 00 001 ... ..... 1 .... @pd_pg_rn
+FCMLT_ppz0 01100101 .. 0100 01 001 ... ..... 0 .... @pd_pg_rn
+FCMLE_ppz0 01100101 .. 0100 01 001 ... ..... 1 .... @pd_pg_rn
+FCMEQ_ppz0 01100101 .. 0100 10 001 ... ..... 0 .... @pd_pg_rn
+FCMNE_ppz0 01100101 .. 0100 11 001 ... ..... 0 .... @pd_pg_rn
+
### SVE FP Accumulating Reduction Group
# SVE floating-point serial reduction (predicated)