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| author | Peter Maydell <peter.maydell@linaro.org> | 2020-08-03 12:18:48 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2020-08-24 10:15:08 +0100 |
| commit | 4c498dcfd84281f20bd55072630027d1b3c115fd (patch) | |
| tree | 72ea9c8100a6c4070fd343db2dc0ee90a24fecfd /target/arm/sve.decode | |
| parent | a3494d4671797c291c88bd414acb0aead15f7239 (diff) | |
target/arm: Convert T32 coprocessor insns to decodetree
Convert the T32 coprocessor instructions to decodetree.
As with the A32 conversion, this corrects an underdecoding
where we did not check that MRRC/MCRR [24:21] were 0b0010
and so treated some kinds of LDC/STC and MRRC/MCRR rather
than UNDEFing them.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200803111849.13368-7-peter.maydell@linaro.org
Diffstat (limited to 'target/arm/sve.decode')
0 files changed, 0 insertions, 0 deletions