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authorRichard Henderson <richard.henderson@linaro.org>2018-06-15 14:57:14 +0100
committerPeter Maydell <peter.maydell@linaro.org>2018-06-15 15:23:34 +0100
commit792a557847697235037fea30eaaacb9b45b4c9e5 (patch)
tree8198b433d6bd0bcdc05d789fd24f6cc59ea22d73 /target/arm/sve.decode
parentef23cb726dc32375bc2fca7ac3e9f34816f6ee13 (diff)
target/arm: Implement SVE copy to vector (predicated)
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180613015641.5667-8-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/sve.decode')
-rw-r--r--target/arm/sve.decode6
1 files changed, 6 insertions, 0 deletions
diff --git a/target/arm/sve.decode b/target/arm/sve.decode
index 1226867f69..519139f684 100644
--- a/target/arm/sve.decode
+++ b/target/arm/sve.decode
@@ -450,6 +450,12 @@ LASTB_v 00000101 .. 10001 1 100 ... ..... ..... @rd_pg_rn
LASTA_r 00000101 .. 10000 0 101 ... ..... ..... @rd_pg_rn
LASTB_r 00000101 .. 10000 1 101 ... ..... ..... @rd_pg_rn
+# SVE copy element from SIMD&FP scalar register
+CPY_m_v 00000101 .. 100000 100 ... ..... ..... @rd_pg_rn
+
+# SVE copy element from general register to vector (predicated)
+CPY_m_r 00000101 .. 101000 101 ... ..... ..... @rd_pg_rn
+
### SVE Predicate Logical Operations Group
# SVE predicate logical operations