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authorRichard Henderson <richard.henderson@linaro.org>2022-10-24 15:18:50 +1000
committerPeter Maydell <peter.maydell@linaro.org>2022-10-27 11:34:31 +0100
commit65c123fdf577413a7d910e6b07c10e79d118041f (patch)
tree6adee993e59fd3659d1b8f5d314d961aee93c400 /target/arm/ptw.c
parent71943a1e9084dde71cabba5895920f3a0c54de9b (diff)
target/arm: Implement FEAT_HAFDBS, dirty bit portion
Perform the atomic update for hardware management of the dirty bit. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20221024051851.3074715-14-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/ptw.c')
-rw-r--r--target/arm/ptw.c16
1 files changed, 16 insertions, 0 deletions
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index 9941fa0ef9..a1f4ae654f 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -1445,6 +1445,22 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw,
goto do_fault;
}
}
+
+ /*
+ * Dirty Bit.
+ * If HD is enabled, pre-emptively set/clear the appropriate AP/S2AP
+ * bit for writeback. The actual write protection test may still be
+ * overridden by tableattrs, to be merged below.
+ */
+ if (param.hd
+ && extract64(descriptor, 51, 1) /* DBM */
+ && access_type == MMU_DATA_STORE) {
+ if (regime_is_stage2(mmu_idx)) {
+ new_descriptor |= 1ull << 7; /* set S2AP[1] */
+ } else {
+ new_descriptor &= ~(1ull << 7); /* clear AP[2] */
+ }
+ }
}
/*