diff options
| author | Peter Maydell <peter.maydell@linaro.org> | 2017-09-07 13:54:54 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2017-09-07 13:54:54 +0100 |
| commit | 9d40cd8a68cfc7606f4548cc9e812bab15c6dc28 (patch) | |
| tree | 5ea2b0c184445a132503a6ae8b8710be0e709fac /target/arm/machine.c | |
| parent | ecf5e8eae8b0b5fa41f00b53d67747b42fd1b8b9 (diff) | |
target/arm: Make CCR register banked for v8M
Make the CCR register banked if v8M security extensions are enabled.
This is slightly more complicated than the other "add banking"
patches because there is one bit in the register which is not
banked. We keep the live data in the NS copy of the register,
and adjust it on register reads and writes. (Since we don't
currently implement the behaviour that the bit controls, there
is nowhere else that needs to care.)
This patch includes the enforcement of the bits which are newly
RES1 in ARMv8M.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1503414539-28762-17-git-send-email-peter.maydell@linaro.org
Diffstat (limited to 'target/arm/machine.c')
| -rw-r--r-- | target/arm/machine.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/target/arm/machine.c b/target/arm/machine.c index 666655d870..d740e83939 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -117,7 +117,7 @@ static const VMStateDescription vmstate_m = { VMSTATE_UINT32(env.v7m.vecbase[M_REG_NS], ARMCPU), VMSTATE_UINT32(env.v7m.basepri[M_REG_NS], ARMCPU), VMSTATE_UINT32(env.v7m.control[M_REG_NS], ARMCPU), - VMSTATE_UINT32(env.v7m.ccr, ARMCPU), + VMSTATE_UINT32(env.v7m.ccr[M_REG_NS], ARMCPU), VMSTATE_UINT32(env.v7m.cfsr, ARMCPU), VMSTATE_UINT32(env.v7m.hfsr, ARMCPU), VMSTATE_UINT32(env.v7m.dfsr, ARMCPU), @@ -271,6 +271,7 @@ static const VMStateDescription vmstate_m_security = { VMSTATE_UINT32(env.pmsav7.rnr[M_REG_S], ARMCPU), VMSTATE_VALIDATE("secure MPU_RNR is valid", s_rnr_vmstate_validate), VMSTATE_UINT32(env.v7m.mpu_ctrl[M_REG_S], ARMCPU), + VMSTATE_UINT32(env.v7m.ccr[M_REG_S], ARMCPU), VMSTATE_END_OF_LIST() } }; |